======================SILICON_PROCESSING========================== Deposit PSG vapox APCVD atmossheric pressure Deposit PSG vapox LPCVD low pressure Deposit PSG vapox vt drift act eng 1.2ev less than 1mV drift with delta 5v stress contact potential (kt/q)*ln(A ) 680 at E20 25C facter 10 less time to fail [100] MOS has lowest surface states ^ z /|\ | [100] PLANE | | __|____ | |____|_____\ | / | / y |/______| /1 ^ |/_ |___ Crystal plane [111] Highest tensile strength Highest density of attoms ^ z /|\ | 1 [111] PLANE |\ /| \ | | \ | |___\______\ / / _- 1 / y |/_- /1 |/_ x [110] Early Bipolar ? x ^ z /|\ | [110] PLANE | _- |_- | _-| | | |____|_____\ | / _- 1 / y |/_- /1 |/_ x [001] Early Bipolar ? ^ z [001] /|\ | _ [111] | /| | |__________\ / / y [010] / |/_ x [100] : Miller indices important planes in a cubic crystal. ___________ / / |_____________ |____________ /| /| / ___/| /\ | / | [001] / | /| __/ | /| \ | / | / | / |___/ | /|| \_ | /___________/ | /__/ | / || \ | | | | | // | | / /| \ | | | |010| /| | [110] | /| | | \_ | | | | | | | | | | | \ | | |_______|___| | | | | / | [111] \ | | / | / | |___________|_ || |________ _\| | / | / | / __/ || / ___ | / [100] | / | / ___/ || / ___ |/ |/ | / ___/ |// ____ |___________| |/__/ |/___ |/ // MOS devices fabricated on (100)-wafers smallest surface state densities on such orientations. ___________ / / /| /| / | [001] / | / | / | /___________/ | | | | | | | |010| | | | | | |_______|___| | / | / | / | / | / [100] | / |/ |/ |___________| tensile strength silicon highest <111> highest density of atoms. oxidize more rapidly than (100)-planes, |____________ /\ | /| \ | /|| \_ | / || \ | / /| \ | /| | | \_ | | | | \ | | / | [111] \ | || |________ _\| || / ___ || / ___ |// ____ |/___ // Silicon Crystal Diamond structure _ , _ ( ) . _ , (_) ' _ (_) / (_) ` : (_)/ \/: : . : \/ ,(_)_ : . : (_)-_ : -_ : : _(/) -_ _(_) : : (_)/ (_) | : : \/ : \| : : (_)_ (_)_(_): : / -_.` _-- . \: :/ . ` (_) (_) (_)` _ . . ` (_) . . ` . dopant and contaminant concentrations in silicon. atoms/cm', about 5e22 Si atoms/cm3 in single crystal silicon, impurity concentration of 5x1016 /cm3 equals 1 ppma SINGLE CRYSTAL SILICON polycrystalline material short minority carrier lifetimes, defects occurring at grain boundaries method obtaining such single crystal Si for VLSI fabrication, 1) Raw material (e.g. quartzite, a type of sand), refined by multi-stage process which produces electronic grade polysilicon (EGS), 2) polysilicon used to grow single crystal silicon by Czochra!ski (CZ) crystal growth or float zone (Fz) growth. Single crystal silicon commercially available in either(100) or (llI)-orientations (other orientations (110) obtained on special order ). Ct growth single crystal ingots are pulled from molten silicon contained in a crucible. Czochralski silicon preferred can withstand thermal stresses better than FZ materia1 is able to offer internal gettering mechanism Float zone crystals, because grown without making contact to any container or crucible, can attain higher purity land thereby higher resistivity) than CZ silicon. Devices and circuitsneed high purity starting material (e.g. high voltage, high power devices) are typically fabricated from FZ silicon. (EGS) Electronic Grade Polysilicon Single crystal silicon grown from melts of electronic grade polycrystalline to achieve controlled doping during single crystal growth, EGS in the parts per billion atoms (ppba) raw material which EGS is refined (quarzite), contains high levels of impurities (e.g. aluminum levels of -3x1020 lcm3 refining process reduce impurities by approximately eight orders of magnitude refinement procedure involves four major stagesS: Reduction of quartzite to metallurgical grade silicon (MGS) with a purity of approximately 98%, Si02 in form of quartzite reacted with carbon to yield silicon and carbon monoxide: Si02 + 2C => Si + 2C0 Quartzite is relatively pure form of Si02 presence of coal, coke, or wood chips) reduced to MGS. name MGS derived from fact this purity sufficiently refined as an alloy material in manufacture of aluminum or for producing silicone polymers. only a small fraction refined into EGS quartzite, coal (or coke), wood chips (for porosity) loaded into submerged elecuode arc furnace electric arcs exceed 2000'C, in those regions SiC formed. SiC reacts with Si02 to form Si, SiO, and CO. silicon is drawn while SiO and CO gases escape through the spaces created by the presence of the wood chips. Large quantities of electrical power are consumed in Conversion of MGS to trichlorosilane (SiHC13), trichlorosilane (SiHC13) formed by reaction of anhydrous hydrogen chloride and MGS. MGS is first ground to a fine powder. powdered Si is then treated with HCI to form SiHC13. reaction of solid Si and gaseous HC1 occurs at 300'C in presence of a catalyst. Both formation of SiC13 and chlorides of impurities (e.g. AIC13, BC13) takes place in this step. resultant SiHC13 is a liquid at room temperatures (boiling point 31.8'C), hence can be purified by distillation. Purification of SiHC13 by distillation, SiHC13 separated by fractional distillation. Upon conclusion SMC13 is highly refined SiHC13 must be deposited as semiconductor grade polysilicon, then converted to single crystal silicon, to determine the impurity levels. (CVD) Chemical vapor deposition Si from purified SiHC13, as EGS highly purified SiHC13 converted into polycrystalline silicon (EGS) by CVD in the presence of hydrogen. process takes place in a reactor (Fig. 5b) first proposed referred to as the Siemens process. 2SiHC13 (gas) + 2H2(gas) => 2Si (solid) + 6HCI (gas) (2) starting surface is a thin silicon rod (called a slim rod) a nucleation surface for depositing silicon. large rods (200 mm idiameter and several meters long) deposition takes several hundred hours. After deposition, EGS processed into three products: a) one-piece crucible charges; b) nuggets (random sized pieces); c) poly-rods (Fig. 6). first two used as charges in CZ growth rods used for float-zoning single crystal ingots. To evaluate the purity of EGS conversion to single crystal silicon by FZ technique, primary flat usually positioned relative to crystal direction. primary flat orientation found using x-rays, to produce a Laue photograph used for several Automated wafer handling equipment to obtain correct alignment, devices on wafer can be oriented to crystal direction with flat as reference. Smaller flats are called secondary flats, utilized to identify orientation and conductivity type of the wafer Since automated equipment relies on the flats flat dimensions precisely machined. sawing operatio ingot rigidly mounted Wafers of <100> orientation normally cut "on orientation" <111> wafers generally cut "off orientation for epitaxial processing applications damaged and contaminated layer is chemically etched away A relatively non-porous and clean wafer backside also produced by this step. wet etch procedure typically etchant solution of hydrofluoric, nitric, and acetic acids chemical-mechanical polishing" step used to produce reflective, scratch, damage free surface accomplished by mounting unpolished slices onto a carrier, then putting on polishing machine. a powered platen drives a polishing pad material across the wafer surface. colloidal silica sluny of sodium hydroxide and fine (-100A) Si02 particles, is dripped onto the table. frictional heat of sliding mounted wafers causes sodium hydroxide to oxidize silicon (i.e.the chemical part of the process). oxide is abraded away by silica particles (i.e. mechanical part). Following polishing cycle which 25 Lm removed) wafers subjected to series of chemical dips and rinses to remove polish slurry. cleaning process concludes this step. Another option being offered is a layer of polysilicon or mechanical damage on backside of wafers for extrinsic gettering purposes (RTP) rapid thermal processing a relatively new technique thermal steps utilized in many other processes that an Gettering term used to describe a variety of processing techniques that remove harmful defects or impurities from regions on wafer which devices fabricated. CMOS process flow Active area formation P and N well implant Gate formation + polycide (optional) NLDD, PLDD implant Spacer formation Source and drain implant Salicide formation (can be replaced by polycide) Dielectric formation Planarisation (optional, with CMP) Contact formation Metal layer/Dielectric/Planarisation/Via contacts Previous steps are repeated 3-7 times Passivation Bond pad opening Electrical testing Future trends Smaller geometries Low voltage circuits Flash, EEPROM, One Time Prog, Multi Time Prog Copper with/without Damascene damascene process damascene process, and dual-damascene process, should be commonplace for 0.18 - 0.13um, and dual-damascene for 0.13-0.10um. greatest advantage is that metal etch steps, notorious for process problems (corrosion,resist burn, time critical with resist, etc) nolongerexist, all patterning done with dielectric etching previously ususable metals,like Copper reconsidered. Single Damascene metal lines are not etched, but deposited in "grooves" within the dielectric layer, then excess metal is removed by CMP. Dieletric 1 deposition CMP planarization Via pattern + etch, resist removal Optional barrier layer deposition Metal plug fill + etchback (steps to obtain drawing 1) Dielectric depo Metal pattern (steps to obtain drawing 2)+etch (dielectric 2 etch only) resist removal Optional barrier layer deposition Metal lines depo (steps to obtain drawing 3) Metal CMP (steps to obtain drawing 4) Dual-Damascene: plugs are filled at the same time as metal lines, below is the current prefered method, since the thickness of the metal lines can be accurately controlled. Dielectric deposition #1 CMP planarization (final thickness is the depth of the Via) Nitride deposition Photoresist for Vias Nitride etch (steps to obtain drawing 1), resist removal Dielectric deposition #2 CMP planarization (final thickness is the depth of the metal lines) Photoresist for Vias and metal lines steps to obtain drawing 2) Dielectric etch, where high selectivity of Dielectric / Nitride is needed, to stop on Nitride for the metal lines (steps to obtain drawing 3) Barrier layer depo Metal plug and lines depo (steps to obtain drawing 4) Metal CMP (steps to obtain drawing 5) Copper for smaller Time delays Time delay where r is resistivity of material, A cross-sectional area of metal lines) and Capacitance (C depends on k / d, speed of current devices is limited by metal layers, where the resistance is from the metal used (currently W and Al / AlCu alloys), and capacitance is from dielectric insulation can also be limited by transistor dimensions, and particularly gate oxide thickness, but these are very small in advanced processes. Metal Resistivity Dielectric material e Tungsten/Alum 4.0 Silicon dioxide Thermal=3.9,PECVD=4.2 Aluminium 2.4 Fluorinated SiO2 3.5 Copper 1.7 Inorganic polymers(MSSQ) 2.7 - 3.5 The current usage of Al/Cu alloys (oreven W for the first metal layer) and silicon dioxide presents barriers to >1GHz speeds or Gbit DRAM or >1billion transistors. Processing challenges Metal deposition The deposition of the metal is made difficult since there is a need to fill holes and trenches, a requirement previously non-existent. Older PVD techniques were able to be used for low aspect ratios (holes which are not very deep or which are wide), but not sufficient for the requirements of new designs. Copper deposition to fill high aspect ratio holes and trenches now proposed by several equipment suppliers. It may be preferable to deposite the seed layer immediately the barrier layer, to prevent oxidation of the barrier layer, for some barrier technologies. This is best handled in a cluster tool, ensuring that the copper seed layer is atomically smooth to allow the ocrrect grain growth during the bulk copper deposition step. Some manufacturers are pushing MOCVD, an UHV chamber with liquid source vapour delivery, which can be clustered with other chambers to provide a complete solution for an integrated PVD barrier layer depostion, RTP, and copper deposition module. Others are pushing more classic tools with PVD copper seed layer deposition. ElectroChemical Deposition, ECD, is a promising bulk copper deposition process, where wafers are submerged into a chemical solution with Copper ions, and electrical reduction of the ions causes them to solidify on the wafers. The advantages of this technique are the low temperatures used, which would be compatible with future polymer dielectrics. Barriers Copper is an excellent diffuser in silicon dioxide, requiring an impermeable barrier. Field isolation techniques The techniques for isolating transistors have evolved over the years, first to diversify, and for the future to focus on a single technique. LOCOS LOCOS: LOCal Oxidation of Silicon Semi-recessed. The classic LOCOS, with an initial oxide, then a nitride layer (Si3N4), and a mask to expose the field oxide areas. The nitride layer is selectively etched to expose the underlying silicon, followed by a thermal oxidation to grow a thick oxide (called Field OXidation, FOX), which can isolate transistors (pictured above). The remaining nitride layered areas are removed, to reveal the ACTIVE area, where the transistors will be formed. Fully recessed. This technique creates a flat topography after the FOX, by etching into the Silicon jsut prior to the FOX. Thermal oxidation causes increase volume (Si+O2-> SiO2), so that the active areas and the locos areas end up at the same height. Deep mesa. Similar to fully recessed technique, except that the silicon etch is deeper. This results in the active areas being higher than the locos areas. Bird s beak Problems with LOCOS Bird s beak. during FOX, a triangular oxide is formed under edges of nitride layer, resembling a bird s beak. cause poor gate oxide quality close to the locos. The problems with FOX become apparent when the mask opening (the width of the area which is not protected by the nitride before the FOX) becomes small (less than 1.5um). The oxide growth achieved in the same FOX process then depends on the width of the opening, effectively becoming thinner with decreasing widths. This effect is called FOX thinning. This causes problems with controlling eletrical parasites, small current which can pass under insuficiently thick locos areas, from one transistor to another. The improvement Locos techniques below have enabled Locos to used for all technology generations down to 0.35um, but combination of [small] bird s beaks (as small as 0.1um with some techniques) and FOX thinning, have limited the choice to one technology, STI. Improvements used with LOCOS PBL The most common improvement is Poly Buffered Locos, PBL, where thin layer of oxide (pad oxide), then poly-Silicon, then a nitride layer is used as the mask for the FOX. active areas are completely etched down to silicon wafer. The result is to reduce stress in the oxide, and reduce the bird s beak. The oxide helps to provide the stop for the silicon etch process (which would otherwise etch into the silicon wafer, resulting in poor gate oxide quality). Sealed PBL, a further improvement of PBL, involves the same flow as PBL, but just before the FOX, an oxynitride layer (SiOxNy, where x and y can vary according to the process) is used to prevent oxidation into the poly-Si layer. The oxynitride is etched from the locos areas before FOX. Suppressed Locos, where the pad oxide layer is replaced by an oxynitride. SILO Sealed Interface Local Oxidation, , is also known, where first step is a nitridation of silicon surface, by exposing the surface to N2O or NO at high temperatures, followed by the usual oxde and nitride steps. Poly Encapsulated Local OXidation, PELOX, PELOX, is similar to suppressed Locos, but involves a poly-Si layer instead of the oxynitride. SWAMI SideWAll Masked Isolation, SWAMI. Single Si3N4 Spacer Off-SEt Local Oxidation, SSS OSELO SSS OSELO, appears promising, but is still STI in evaluation status. STI, Shallow Trench Isolation Originally developed by IBM, it has been in limited use by many manufacturers for 0.5um and 0.35um. It is now the Field Isolation option of choice for 0.25um and below. The processing steps are as follows: Thermal oxidation (furnace, pad oxide), deposit nitride(furnace,LPCVD) Active mask (lithography), trench etch (dry etch, nitride + oxide + silicon etch), resist strip (dry, wet) Thermal oxidation, to remove damage from silicon etch (furnace, high temp) Deposit silicon oxide to fill trench (dielectrics, High Density Plasma, or furnace, LPCVD) Oxide densification (furnace, high temp) Inverse active mask (lithography), oxide etch (dry etch), resist strip (dry, wet), to flatten layer CMP oxide removal, stop on nitride layer, resulting in a flat topography (pictured above) Nitride removal (wet etch) to reveal flat, un-damaged active area, for transistor formation Problems can occur when the final isolation oxide level is lower than the active area, where the gate oxide will be grown. The Semiconductors Network. Resistance p*(1+aT) ohms*m 1/ C Alum 2.63E-8 0.0039 Carbon 3.5E-5 -0.0005 Copper 1.72E-8 0.00393 Silver 1.47E-8 0.0038 Gold 2.44E-8 0.0034 Glass 10E10-10E14 Air DIELECTRIC 1 Glass DIELECTRIC 5-10 TiO DIELECTRIC 173 Wood $1/Therm Gas $0.4/Therm Electric $2.70/Therm Therm 27.77KWHR high doping levels mobility decreases additional scattering from impurity high electrifields mobility also decreases, carriers at limiting velocity almost independent of field. limiting velocity is of order of ~10e6cm/ sec. recombination rate for excess electrons in p material, dn/dt= -(n-n_0)/tau_n no is the equilibrium density and tau_n, is called the lifetime of electrons. excess decays as exp (-t/tau_n). Lifetime very sensitive puritles several microseconds down to few nanoseconds. Lifetime can be reduced for such applications by introducing impurity atoms (such as gold) which act as recombination centers. silicon latin silex or silicis meaning flint. 25.7% of the earths crust. invent transistor Bardeen, Brattain, and Shockley in 1947. Germanium (Ge) original semiconductor material used to fabricate diodes and transistors. narrow bandgap of Ge (0.66 eV),relatively large leakage Germanium oxide (Ge02) could act as such a layer but it is difficult to form, is water soluble, and dissociates at 800'C. larger bandgap of silicon (1.1 eV) smaller leakage currents maximum operating temperature of 150'C. Si02 easy to form chemically very stable. electronic grade silicon is about one tenth as costly as germanium. Package_Thermals silicon (physical data) Atomic number: 14 Atomic weight: 28.086 Density: 2329 [293 K];2525 [at m.p.] kg m-3 Molar volume: 12.06 cm3 Velocity of sound: 2200 m s-1 Hardness Mineral: 6.5 Melting point: 1683K Boiling point: 2628K Thermal conductivity: 148 [300 k] W m-1 K-1 Water Standard: 2.42W Specific Heat: 0.76joule/gm*C Fusion: 39.6 kJ mol-1 Vaporization: 383.3 kJ mol-1 Linear Hole Mobility Melt Coeff Eg Electron ======================ELECT_BREAKDOWN_V==================== ------------------------------------------------------------- expansion 46E-6 delta_L/L per C Si 1.00 ->1.46 Watts/cm*C GaAS 0.44 Cu 4.05 Gold 3.09 Silver 4.14 Kovar 0.2 BeO 2.34 saphire 0.25 Al2O3 0.188 ------------------------------------------------------- Heat + - ___ _|HOT| _|_ | | Holes are dominate \ / \ / have energy _____V_______________V_______ want to move out Psub <--- holes Light / excess minority carriers /_ diffuse into other areas _______/____ Psub electrons ---> (ni)^2 = N_p*electrons Resistance (ohms/square) versus doping 100 ................................................ | p . . . . . . | |n . . . . . . | | n . . . . . . | | . . . . . . | 10|....n..p........................................| | . . . . . . | | . p . . . . . | | .n . . . . . | | . . . . . . | 1|..........n...p.................................| | . . . . . . | | . . p. . . . | | . .n . . . . | | . . . . . . | .1| ................n.......p......................| | . . . . . . | | . . . n . . . | | . . . . p . . | | . . . n. . . | .01|...............................n..p.............| | . . . . . . | | . . . . .n . | | . . . . . p . | | . . . . . p | .001|.........................................n......| | . . . . . . n | | . . . . . . p n| | . . . . . . p | | . . . . . . p| .0001|________________________________________________| E14 E15 E16 E17 E18 E19 E20 E21 doping( /cm^3) Mobility (cm/sec)*(cm/V) versus doping ................................................. | . . . . . . | | . . . . . . | | . . . . . . | |e e . . . . . | 1000 |.............e..................................| | . . . . . . | | . . . . . . | | . . e . . . | | . . . . . . | |h...h...........................................| | . h . . . . . | | . . h . .e . . | | . . . . . . | | . . . . . . | 100 |.........................h.........e............| | . . . . . e e | | . . . . . . | | . . . . h . . | | . . . . . h h | |................................................| | . . . . . . | | . . . . . . | | . . . . . . | | . . . . . . | 10 |________________________________________________| E14 E15 E16 E17 E18 E19 E20 E21 doping( /cm^3) together with other carbon _ / \ '| | \ ' | | ___ '___\ /'___) (___/ | ` ' -_ \ \ ' - \_| The four covalent bonds of carbon Silicon Crystal Diamond structure _ , _ ( ) . _ , (_) ' _ (_) / (_) ` : (_)/ \/: : . : \/ ,(_) : . : (_)-_ :` _ : : _(/) -_:_(_) : : (_)/ (_): : : \/ : `:_ : : (_)_ (_)_(_): : / -_.` _-- . `: :/ . ` (_) (_) (_)` _ . . ` (_) . ======================SILICON_DEFECTS===================== Various crystal defects in a simple cubic lattice a) interstitial impurity ion | | | | | | | -0--0--0--0--0--0--0- | | | |A | | | -0--0--0--0--0--0--0- | | | | | | | -0--0--0--0--0--0--0- | | | | | | | edge dislocation | | | | | | | -0--0--0-0-0--0--0- | | \ / | | -0--0--0--0--0--0--0- | | | | | | -0--0--0--0--0--0--0- | | | | | | self-interstitial | | | | | | -0--0--0--0--0--0--0 | | | |0 | | -0--0--0--0--0--0--0- | | | | | | | -0--0--0--0--0--0--0- | | | | | | | coherent precipitate of substitutional atoms | | | | | | | -0--0--A--A--A--0--0- | | | | | | | -0--0--A--A--A--0--0 | | | | | | | -0--0--0--0--0--0--0- | | | | | | | small dislocation loop formed by agglomeration of self-interstitials | | | | | | | -0--0--0-0-0--0--0- | | \ A / | | -0--0--0--0--0--0--0- | | | | | | -0--0--0--0--0--0--0- | | | | | | substitutional atom widening the lattice | | | | | | | -0--0--0--0--0--0--0- | | | | | | | -0--0---0-A-0---0--0- | | | | | | | -0--0--0--0--0--0--0- | | | | | | | vacancy | | | | | | | -0--0--0--0--0--0--0- | | | | | | -0--0--0 0--0--0- | | | | | | -0--0--0--0--0--0--0- | | | | | | | small dislocation loop formed by agglomeration of vacancies | | | | | | | -0--0--0-0-0--0--0- | | \ / | | -0--0--0--0--0--0--0- | | | | | | -0--0--0--0--0--0--0- | | / \ | | -0--0--0-0-0--0--0- | | | | | | | substitutional impurity atom compressing the latticelO | | | | | | -0--0--0--0--0--0--0- | | | | | | | -0--0-0---A---0-0--0- | | | | | | | -0--0--0--0--0--0--0- | | | | | | | Point defects 0 0 0 0 0| 0 0 0 0 0 0 0 | 0 0 0 0 0| 0 0 0 0 0 0 _ 0 0 0 _/ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Schottky defect ___ 0 0 0 0 0 0 0 0 0 0/ 0 0 0 0 0 0 0 0 0 0 0 |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 interstitial arriving from surface 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --- > 0 0 0 0 / 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c) Frenkel defect. Intrinsic point defects important in kinetics of diffusion. diffusion of many impurities depends on the vacancy concentration. low packing-density of the diamond lattice (34% versus 74% for a fee lattice) implies large spaces between atoms (interstices) which atoms of same size can be placed without shifting of neighboring atoms structural condition of the silicon lattice favors incorporation of interstitials, why Si lattice fewer vacancies than metal lattices self-interstitial | | | | | | -0--0--0--0--0--0--0 | | | |0 | | -0--0--0--0--0--0--0- | | | | | | | -0--0--0--0--0--0--0- | | | | | | | extrinsic point defects, involving foreign atoms. non-Si atoms occupy lattice sites, defects referred to as substitutional impurities. bonafide point defects, atoms are larger or smaller crystalline regularity perturbed. substitutional atom widening the lattice | | | | | | | -0--0--0--0--0--0--0- | | | | | | | -0--0---0-A-0---0--0- | | | | | | | -0--0--0--0--0--0--0- | | | | | | | Impurity also occupy non-lattice sites, called interstitial impurities. | | | | | | -0--0--0--0--0--0--0 | | | |A | | -0--0--0--0--0--0--0- | | | | | | | -0--0--0--0--0--0--0- | | | | | | | To be electrically active, atoms usually must be located on lattice sites. inherent solubility of impurity in silicon crystal. is a maximum specific concentration depends on the element and temperature solubility most impurities increases up to a temperature, then decreases as approaches its melting point. known as retrograde solubility. dislocations form by growth and multiplication of dislocation loops in the bulk, or from dislocations generated at the surface in response to stresses created in crystal. edge dislocation | | | | | | | -0--0--0-0-0--0--0- | | \ / | | -0--0--0--0--0--0--0- | | | | | | -0--0--0--0--0--0--0- | | | | | | Stresses can arise i a) diff expansion due to temp variations in crystals''; b) intro substitutional impurities cause stresses between doped and undoped crystal regions called misfit dislocations.); c) compressive stresses from volume mismatches arise during some precipitation events d) coefficient of thermal expansion stresses caused by layers present on surface of crystal7 involves growth of thermal oxide and suppression of oxidation on other by nitride layers. Dislocation causing stresses result primarily from tensile stress silicon nitride, and volume expansion of oxide formed in walls.) stresses arise in a variety of ways seed crystals undergo high thermal stress when immersed into Si melt during single crystal ingot exterior of seed crystal is brought to melt temperature, interior much cooler. Stresses resulting from expansion at surface and interior of seed crystal induce dislocations lead to plastic deformation of crystal. (Plastic deformation is permanent deformation of material that remains after stress released. Elaitic deformation, lost upon release of stress. Plastic deformation occurs when elastic limit [or yield strength] is exceeded.) Dislocations in wafers induced by thermal stress during furnace operationss. Upon removing wafers from furnace, edges of wafers cool faster wafers are held vertically and spaced closely in wafer boats. edges radiate heat to cooler surroundings stress S from uneven cooling S = cr ff T cr= coeff thermal expansion silicon 4e6 cm /cm'K, ff= Youngs modulus ( 1.5 x 1012 dyn lcm2, T = temperature difference between edge and center (temperature gradients in cooling wafers can reach >150'C). If stress exceeds yield strength dislocations will form. stress from 150'C gradient 0.9 x 10' dyn lcm2, larger than yield strength (0.45e9 dyn /cm2 850'C, thus introduce dislocations. yield strength of CL Si wafers is impacted by the presence of impurities, as oxygen. Dislocations can climb and glide. Climb occurs when point defects are absorbed by the dislocation line. Thus, if a self-interstitial is captured, an edge dislocation moves as shown in Fig. 5a, while the absorption of vacancy causes line to climb in opposite direction. Dislocation loops also change size by climb-type events (absorption of point defects). Movement of the dislocation in the surface defined by its line and | _____| |/ | | | | | | | | | | | | . ._/ |. _- | - Typical characteristics of single-emitter test transistor (emitter area 3 x 8 m) with emitter collector short showing up in ICEO IVCE (---) ICE /VCB ( ). and IEB IVEB (...) are "hard"57 _________ p / ___/____ _________ n | / p \/_____ ___/____ _________ n | \/___ n \/_____ p ___/____ b) Schematic of enhanced emitter diffusion model explain collector-emitter pipe formation CRYSTAL DEFECTS ON DEVICE PROPERTIES T influenced by crystalline defects include: a) leakage currents in p-n junctions; b) collector-emitter leakage currents in bipolar c) minority carrier lifetimes; d) gate-oxide quality; e) threshold voltage uniformity in MOS devices; f) resistance to warpage wafers during thermal process Leakage Currents precipitates and dislocations increase pn junction leakage. transition metal precipitates in pn junction produces leakage due to mid-gap energy levels at low voltages, and a "soft" leakage component at higher voltages Dislocations and thereby extrinsic stacking faults that cross pn junctions, The formation of generation-recombination (g-r) centers defect sites junctions, and the decoration of dislocations Collector-to-emitter leakages have been correlated with dislocations from emitter to collector. If dislocation decorated with metallic impurities, permit significant current between collector and emitter dislocation role in enhancing diffusion along dislocation during emitter formation can lead to emitter-collector pipes, precipitates contributes to locally retarded dffjsion of dopant atoms in shallow double-diffused structures. dopant appears not to diffuse as rapidly in region of precipitate, forming a localized spike pointing upward toward the wafer surface2 precipitate apparently dissolves during first diffusion. second diffusion is thus effected by precipitate, locally narrow separation of emitter and collector at spike causes excessively large reverse currents. not expected to occur in ion-implanted devices. Minority Carrier Lifetimes mean time spent before they recombine Gate Oxide Defects in silicon subscrate MOS devices: 1) oxide leakage current; 2) oxide breakdown voltage. both correspond to stackig faults at silicon substrate generated by metallic contamination during oxidation. correlate with high defect density on wafer surface. ------------------------------------------------------- tau_p 1/(sigma_p*v_th*N_t) lifetime in low level injection N_t concention of centers of recombination v_th sqrt(3*k*T/m) = ~ 1e-7cm/sec thermal velocity sigma_p capture cross section n N_c*exp( (E_c - E_f)vt) p N_v*exp( (E_f - E_v)vt) Fermi Dirac 1/(1+exp( (E - E_v)vt) ) Fermi Dirac distribution n_i^2 N_c*N_v*exp ( -E_g/vt) intrinsic carriers Phi_Fn vt*ln(N_D/n_i) Phi_Fp vt*ln(N_A/n_i) Phi_T Phi_Fp + | Phi_Fn | built in pn junction V q*C_B*W^2/(2*K_s*e_0) W sqrt( 2*K_s*e_o*Phi_T/(q*N_A) ) depletion width I_R I_gen + I_sh + I_surface reverse leakage I_gen q*n_i*W*Area/tau_g generation leakage funct_of 1/tau_g funct_of Num_traps I_gen(V) I_gen_0*sqrt(V) from W I_gen(T) I_gen_0*exp(-E_g/(2*K*T)) from ni I_sh (q*n_i^2*Area/N_D)*sqrt( D_n/tau_r) shockley component funct_of sqrt(Num_traps) "diffusion current" I_sh(T) I_sh_0( -E_g/( K*T)) n_i ni_i_0*exp(-E_g/(2*K*T)) T_c when I_gen(T) = I_sh(T) at or below room D_n v_t/mu_n 34cm2 diffusion coefficent v_t K*T/q thermal voltage mu_n 1300cm^2/V-s @ room mobility D_p v_t/mu_p 13cm2 diffusion coefficent mu_p 500cm^2/V-s @ room mobility L_p sqrt(D_p*tau ) diffusion length tau 34u -> 2000u lifetime I_surface 4e9/cm2-V about surface state leakage n n n n n n ____________ Ec ............ Ef N type _____________Ev p n n ____________ Ec ............ Ef P type _____________Ev p p p p p p Ef Fermi Potent where prob of electron is 50% f(E) 1/(1+exp( (E-EF)/KT )) Tau TF = Wb^2/(2*Diff_b) vt KT/q Thermal energy KT/q Diffion/mobitity ======================SILICON_BREAKDOWN=========================== watch cap Breakdown see flashes as filaments as increase voltage burn out.. start at edges towards center %_of_Isat At given voltage given percent Isat forms holes/electrons I_leakage Isat + Isat*P% + Isat*P%^2+.. Isat/(1-P%) P% (V/Vbeakdown)^3 I_leakage Isat/(1- ( (V/Vbeakdown)^3 ) ) Pbeta% (Beta+1)*P% if beta get into the picture Vcbo Vcbo/((1+Beta)^sqrt(1/3)) Breakdown BVbco_V 95*(rho_epi_ohm_cm)^(.722) BVceo_V BVbco_V/( (Beta_max+1)^(.25) ) BVbco_TLV 36*(w_um)^(.861) BVbco_thickLimited_V