======================COMPUT_HIST=============================== POKE command could make monitor of PET computer catch fire poke controlled size of screen for electron beam setting to Zero meant entire screen in center burning out the phosphor on the monitor. old CD ? Microwave it. Put in the microwave oven, above a cup turned upside down (the cup, not disk), set power to HIGH, the timer to 5 seconds, turn off all the lights, make sure you watch. You will never use this CD again. microwave oven is left apparently intact. cat printed on motherboard of Sun SPARCStations IPX It is supposed to be comic strip caracter "Hobbes" (from Calvin and Hobbes). The Sun internal name for the IPX is "Hobbes" (the SparcStation 2 is Calvin). IBM choose 8088 rather than 68000 as processor for their first PC? IBM PC supposed to be low-end model machine compete with CP/M machines and Apple II, needed a 16-bit CPU, but not too much memory. With 8-bit data bus, 8088 cheaper hardware limited address space (1MB, reduced by IBM's to 640 KB) wasn't perceived as a problem 8088 allowing easy proting of 8080/Z80 code. lots of software could be produced very by porting existing CP/M programs Microsoft Basic and WordStar 8088 processor really code compatible with the 8080? No, not on the binary level; opcodes different. However, the instruction sets are so similar that assembly language programs can be machine translated from 8080 assembler to 8088 assembler. VAX mean? Why did early VAXen have model numbers starting with "11",like 11/780, 11/750, and so on? Rumour has it that 11/780 was originally intended as PDP 11/78 with "Virtual Address eXtension" (i.e. virtual memory), but Digital choose to present their new 32-bit line of computers under the name "VAX" rather than"PDP". The 11/xxx series of VAX machines all had a special "compatibility mode" in which they can run PDP-11 code. FORTRAN variable integer if in range I-N first two letters INteger but math using 'i' in equations as sample variable ___ \ /__ X i=0 i and FORTRAN obviously stole the idea from us. Apple uses Cray to do heavy calculations, Cray probably uses Macs in CAD, Bill Gates Microsoft bought MS-DOS from a Seattle company, and it was called QDOS then (Quick and Dirty Operating System). Is '2' the lowest possible numeric base ? No. possible to usenon-integral, negative, irrational, or even complex bases. viruses in printers during Gulf War? This is an excerpt from the January 20, 1992 issue of "U.S. News and World Report" magazine, sidebar on page 50 entitled "Spy Wars -- The gulf war flu": Several weeks before the air campaign of Operation Desert Storm began, U.S. intelligence agents notched up the odds for the American-led coalition a bit. The agents had identified a French-made computer printer that was to be smuggled from Amman, Jordan, to a military facility in Baghdad, where it was to be used in a computer network critical to the coordination of Iraq's formidable air-defense batteries. They were said to be second only to those of Moscow. According to two senior U.S. officials familiar with these events, this is what happened next. The U.S. agents in Amman replaced a computer microchip in the French-made printer with another microchip provided by the National Security Agency in Fort Meade, Md. Technicians there had designed a computer virus into the tiny electronic circuits of the microchip. The virus was designed to disable a mainframe computer, the officials said, but by attacking through a printer, known as a "peripheral" piece of equipment, it was able to circumvent the electronic security measures designed to protect mainframe computers from such interference. The virus was cunningly designed, and it must have driven Iraq's air-defense computer technicians to distraction. Once the virus was in the system, the U.S. officials explained, each time an Iraqi technician opened a "window" on his computer screen to access information, the contents of the screen simply vanished. The virus seems to have worked as planned, the two officials said. The irony is that it was probably not needed. The coalition's overwhelming air superiority would have ensured pretty much the same result whether the virus had been used or not. ======================COMPUT_PC=================================== Internet: Incredibly slow (1 sec. and 3 days, unlimited size) idea caching use a small amount of expensive memory to speed up slower, less expensive memory. 500 MHz chip through 500 million cycles in one second (1 cycle every 2 nanoseconds). Without L1 and L2 caches, 256k L2 cache caches 64 megabytes of RAM. most programs theoretical concept called locality of reference. only small portions used at any one time. Layers Cache The processor requests a piece of information. first place it looks is in the level 1 cache, If it finds it there (called a hit on the cache), it uses it with no performance delay. If not, a miss and the level 2 cache is searched. If it finds it there (level 2 "hit"), Otherwise, issue a request to readfrom system RAM. Level 1 (Primary) Cache built directly into the processor from 8 KB to 64 KB, also sometimes called "internal" cache Level 2 (Secondary) Cache usually 64 KB to 2 MB in size. usually found on motherboard or daughterboard that inserts into the motherboard. also called "external" cache Disk Cache used to cache reads and writes to the hard disk. PeripheralCache other devices can be cached using the system RAM as well CD-ROMs System Cache Function and Operation memory chips are instead logically organized as a "square" of rows low-order 11 bits are considered the "row" high-order 11 bits the "column". DRAMs are arranged into modules, and then into banks, the memory controller manages which sets of chips are read from or written to. synchronous DRAM uses different timing signals: RAS row address strobe (row address select) When the /RAS signal has settled at zero, the entire row selected is read by the chip. this action refreshes all the cells in that row; refreshing is done one row at a time. DRAM Asynchronous and Synchronous original IBM PC days, asynchronous. memory is not synchronized to the system clock. newer type of DRAM, called "synchronous DRAM" or "SDRAM", is synchronized to the system clock; timing is much tighter and better controlled. much faster than asynchronous DRAM Memory Bus data bus and the address bus. Bottleneck The Processor-Memory memory bus is limiting factor to system performance. Old computers processor running same speed as memory bus newer ones processor running 2, 3 faster than the memory, DRAM Speed, System Timing and Overall Memory Speed true speed memory runs at. The two factors are: Memory Timing Settings: memory's real speed is determined by timing often via settings in BIOS setup program. speed of the DRAM sets the limits if you replace 70 ns DRAM with 60 ns DRAM, the system will not run faster unless you increase the system speed Conventional asynchronous DRAM rated in nanoseconds access cycle. Most asynchronous is 50, 60 or 70 ns in speed. 70 ns is fine for 486 or older PCs. Synchronous memory is much faster usually rated at 12, 10 or even 7 nanoseconds; An SDRAM module rated at 10 ns is not "5 times faster" than an EDO module rated at 50 ns. SDRAM speed ratings refer to maximum speed at which SDRAM module can burst data onto the bus. not include the addressing latency time DRAM chips usually marked with speed via a suffix at the end of the part number. "-6" or "-60". Synchronous DRAM (SDRAM) able to read or write from memory in burst mode (after the initial read or write latency) at 1 clock cycle per access (zero wait states) at memory bus speeds up to 100 MHz or higher improvements including internal interleaving, a half modulebegin access while other half finishing one doesn't offer much "real world" additional performance system cache masking much of that differential in speed, most systems are running on relatively slow 66 MHz or lower system bus speeds. As 100 MHz bus system PCs become mainstream, SDRAM designed to work at these higher Speed Speed Matching: "nanosecond" rating "MHz" rating, "83 MHz" or "100 MHz" SDRAMs conventional EDO and FPM memory. 2-Clock and 4-Clock Circuitry: commonly called 2-clock and 4-clock SDRAMs. almost, differ in how they are laid out and accessed. 2-clock SDRAM each clock signal controls 2 DRAM chips on module 4-clock SDRAM control 4 different chips each. Serial Presence Detect: an EEPROM that contains speed and design information about the module. your board requires SPD... CAS2 vs. CAS3: "CAS" stands for column address strobe, main signals used in accessing DRAM chips; "CAS2" and "CAS3" used to distinguish slight variants in SDRAM modules. "2" and "3" refer to the latency of the CAS line, the terms should be "CL2" and "CL3". Packaging Concerns: To make matters even more confusing, SDRAM usually comes in DIMM packaging, which itself comes in several different formats (buffered and unbuffered, 3.3 volts and 5 volts). Mixing DRAM Speeds PCs read a certain bit width of memory at a time, typically 32 or 64, memory making up this width is called a bank. PCs always read data from more than one chip at a time only use the same type and speed of memory within a bank. also use the same technology-- never mix EDO and FPM memory (for example) within a bank. Slowest Memory Put in the First Bank: Some memory systems automatically look at the speed of the memory in the first bank when setting the timing. Memory Bus Speed and Required DRAM Speed Processor Memory Bus Usual Required DRAM Usual DRAM Technology Generation Speed Speed (ns) First, Second 4.77-20 100-120 Conventional 100-120 Third, Fourth 16-40 70-100 Conventional, Page Mode, FPM,EDO Fifth, Sixth 50-100 8-10 (SDRAM) 50-70 FPM, EDO, BEDO, SDRAM (Asynchronous) Future 125+ ? SDRAM, DDR SDRAM, DRDRAM, SLDRAM, Other? System Timing and Wait States true speed that the memory subsystem runs referred to as the system timing. using a number of settings in the BIOS setup program, normally specified as the number of clock cycles EDO memory is faster than FPM. Burst Mode Access and Timing memory is stored as a matrix; you must address it by supplying the row and column usually, read 32 or 64 bits at a time (64 on modern PCs). row address sent to memory, followed by column address. the data itself is transferred. first access to memory takes a-usually from 4 to 7 clock called the latency of the memory. Four consecutive 64-bit pieces of memory are read one after the other (256 bits or 32 bytes). called burst mode access or bursting. Modern caches also do this type of burst access. timing of burst mode access is generally stated using this type of shorthand: "x-y-y-y". The first ("x") number of clock cycles do first 64-bit read/write. other numbers are how many clock cycles to do the second, third and fourth reads/writes. "5-2-2-2", which means 11 clock cycles for whole burst. System Timing and Memory Technologies FPM fast page mode regular in most Pentium systems, (FPM) memory burst cycle time of 3 clock cycles, while EDO extended data out (EDO) memory will run with only 2 clock cycles. SDRAM will usually require only one clock cycle when bursting. DRAM Technologies and Relative Performance has unfortunately become an exercise in buzzword juggling ESCD Extended System Configuration Data (ESCD) where BIOS settings are held. to hold configuration information for the hardware in your system. At boot time the BIOS checks this area of memory and if no changes have occurred since the last bootup, it knows it doesn't need to configure anything and skips that portion of the boot process. used communications link between BIOS and operating system Boot Block Many newer systems come with a 4 KB "boot block" program is included as part of the BIOS. job to recover from the BIOS code incorrect or corrupted. Date The system date. the correct format; normally this is mm/dd/yy IDE Primary Master where the hard disk parameters are entered for the primary master IDE/ATA device, the first drive in a modern IDE system. Dynamic RAM (DRAM) refresh circuit. Many hundreds of times each second, Memory Access and Access Time A specific procedure is used to control each access to memory, which consists of having the memory controller generate the correct signals to specify which memory location needs to be accessed, a nd then having the data show up on the data bus Speculative Leadoff the first access to memory ("leadoff") by overlapping the start of the read request Interleaving by allowing simultaneous access ROM Shadowing in most PCs, there is a full 384 KB area of RAM in the UMA. When any addresses in the UMA region are used by ROMs, the RAM underlying them is hidden. However, doesn't mean it has to be wasted. access time of ROMs is usually between 120 and 200 ns, compared to system RAM which is typically 50 to 70 ns. RAM is accessed 32 bits at a time, ROMs are usually 16 bits wide. most systems have the ability to "mirror" the ROM code into this RAM to improve performance. called ROM Shadowing,controlled using set BIOparameters HMA High Memory Area (HMA) the first 65,520 bytes (64 KB less 16 bytes) of extended memory. from addresses 100000h to 10FFEFh. the only part of extended memory that can be used by the PC while operating in real mode. Normally in real mode the processor cannot access extended memory at all and must use protected mode or special drivers. Don't confuse high memory area with upper memory area, Intel created the 80286 processor, it supported both protected mode and real mode. in real mode the 80286 was supposed to behave exactly the same as an 8088 or 8086, for compatibility. 80286 does have a 21st address line (it has 24),due to a bug in its design it didn't do the wrap around in the same way as the 8088 when in real mode. used address FFFF:FFFF and came up with 10FFEFh for linear address, kept as 10FFEFh instead of wrapping around to 0FFEFh like on the older CPUs. allowed the first FFEFh of extended memory (100000-10FFEFh) to be accessed by the chip even while still in real mode. This block of memory is the high memory area (HMA). still problem ensuring compatibility of 80286 when in real mode. IBM solved original AT by using spare lines in the keyboard controller chip to manage the 21st address line (called A20 line because address bits are numbered starting with zero). keyboard controller turns off the A20 line when the processor is running in real mode, to allow for full compatibility with the older PCs. It turns it back on when running in protected mode. why sometimes see error message relating to the A20 line when you have a keyboard problem with your PC. Many years later, 640 KB limit of conventional memory quite cramping ability to access an additional 64 KB of memory in real mode was seen as a significant advantage. (People at this time were scratching and clawing to get even 8 KB more conventional memory to let them run large programs that insisted on certain minimums). Microsoft developed a special driver called HIMEM.SYS t allowed A20 line manipulated under software control This allows the high memory area to be put to good use. high memory area is normally used by DOS itself. Specifying "DOS=HIGH" in the DOS system file CONFIG.SYS tells DOS to load a portion of its own code into high memory area instead of conventional memory. frees approximately 45 KB memory for use by programs. final step in institutionalizing this former bug as an official PC feature was removing manipulation of the A20 line from the keyboard controller. was originally a hack anyway the controller used because no better way to do it nothing to do with the keyboard-- FPM Fast Page Mode (FPM) DRAM FPM memory is slightly faster than conventional DRAM. FPM works by sending the row address just once for many accesses to memory in locations near each other FPM DRAM typically allows burst system timings as fast as 5-3-3-3 at 66 MHz. BEDO Burst Extended Data Out (BEDO) DRAM Burst EDO or BEDO memory EDO memory is combined with pipelining technology and special latches to allow for much faster access time than regular EDO. BEDO memory allows use of much higher memory bus speeds BEDO allows system timings of 5-1-1-1 VRAM Video RAM (VRAM) and Other Video DRAM Technologies Modern video adapters use specialized RAM separated from the main system memory. Cache A 512 KB level 2 cache, caching 64 MB of system memory, can supply information s 90-95% of the time. Programs tend to spend large periods of time working in one small area of the code, often performing the same work many times over and over with slightly different data, because of "loops", cache is programmed (in hardware) to hold recently-accessed memory locations each of these instructions saved in cache after being loaded from memory The next time the processor wants to use the same instruction, it will check the cache and load it from cache cache Pronounced cash, smart caching system recognize certain types of frequently used data. RAM disk RAM that has been configured to simulate a disk drive. You can access files on a RAM disk as you would real disk approximately a thousand times ======================COMPUT_PC=================================== Caching Modern computers have both L1 and L2 caches. to accelerate your computer use of a faster but smaller memory type to accelerate a slower but larger memory type. using cache, must check to see if item in the cache. If it is, that is called a cache hit. If not, it is called a cache miss computer wait for round trip from slower memory multiplelayers cache 2-level cache. main memory (RAM), around 60 nanoseconds Microprocessors 2 nanoseconds, build a memory bank 30 nanoseconds 2 times faster called a level 2 cache or a L2 cache. faster memory system built directly into microprocessor's chip? accessed at speed of the microprocessor and not the speed of the memory bus. a L1 cache, 233 MHz Pentium is 3.5 times faster than the L2 cache Cache also be built directly on peripherals. Modern hard disks come with (around 512K) For the computer, these memory chips are the disk itself. L1 cache: Memory accesses at full microprocessor speed (< 10 Ns, 4K to 16K in size) L2 cache: Memory access of type Static Random Access Memory (SRAM) (around 20 - 30 Ns, 128K to 512K in size) Main memory: Memory access of type Random Access Memory (RAM) (around 60 Ns, 32M to 128M in size) Hard disk: Mechanical, slow ( 12 milliseconds, 1G to 10G in size) Internet: Incredibly slow (1 sec. and 3 days, unlimited size) idea caching use a small amount of expensive memory to speed up slower, less expensive memory. 500 MHz chip through 500 million cycles in one second (1 cycle every 2 nanoseconds). Without L1 and L2 caches, 256k L2 cache caches 64 megabytes of RAM. most programs theoretical concept called locality of reference. only small portions used at any one time. Layers Cache The processor requests a piece of information. first place it looks is in the level 1 cache, If it finds it there (called a hit on the cache), it uses it with no performance delay. If not, a miss and the level 2 cache is searched. If it finds it there (level 2 "hit"), Otherwise, issue a request to readfrom system RAM. Level 1 (Primary) Cache built directly into the processor from 8 KB to 64 KB, also sometimes called "internal" cache Level 2 (Secondary) Cache usually 64 KB to 2 MB in size. usually found on motherboard or daughterboard that inserts into the motherboard. also called "external" cache Disk Cache used to cache reads and writes to the hard disk. PeripheralCache other devices can be cached using the system RAM as well CD-ROMs System Cache Function and Operation memory chips are instead logically organized as a "square" of rows low-order 11 bits are considered the "row" high-order 11 bits the "column". DRAMs are arranged into modules, and then into banks, the memory controller manages which sets of chips are read from or written to. synchronous DRAM uses different timing signals: RAS row address strobe (row address select) When the /RAS signal has settled at zero, the entire row selected is read by the chip. this action refreshes all the cells in that row; refreshing is done one row at a time. DRAM Asynchronous and Synchronous original IBM PC days, asynchronous. memory is not synchronized to the system clock. newer type of DRAM, called "synchronous DRAM" or "SDRAM", is synchronized to the system clock; timing is much tighter and better controlled. much faster than asynchronous DRAM Memory Bus data bus and the address bus. Bottleneck The Processor-Memory memory bus is limiting factor to system performance. Older computers processor running same speed as memory bus, newer ones processor running 2, 3 faster than the memory, DRAM Speed, System Timing and Overall Memory Speed true speed memory runs at. The two factors are: Memory Timing Settings: memory's real speed is determined by timing often via settings in BIOS setup program. speed of the DRAM sets the limits if you replace 70 ns DRAM with 60 ns DRAM, the system will not run faster unless you increase the system speed Conventional asynchronous DRAM rated in nanoseconds access cycle. Most asynchronous is 50, 60 or 70 ns in speed. 70 ns is fine for 486 or older PCs. Synchronous memory is much faster usually rated at 12, 10 or even 7 nanoseconds; An SDRAM module rated at 10 ns is not "5 times faster" than an EDO module rated at 50 ns. SDRAM speed ratings refer to maximum speed at which SDRAM module can burst data onto the bus. not include the addressing latency time DRAM chips usually marked with speed via a suffix at the end of the part number. "-6" or "-60". Synchronous DRAM (SDRAM) able to read or write from memory in burst mode (after the initial read or write latency) at 1 clock cycle per access (zero wait states) at memory bus speeds up to 100 MHz or higher improvements including internal interleaving, a half modulebegin access while other half finishing one doesn't offer much "real world" additional performance system cache masking much of that differential in speed, most systems are running on relatively slow 66 MHz or lower system bus speeds. As 100 MHz bus system PCs become mainstream, SDRAM designed to work at these higher Speed Speed Matching: "nanosecond" rating "MHz" rating, "83 MHz" or "100 MHz" SDRAMs conventional EDO and FPM memory. 2-Clock and 4-Clock Circuitry: commonly called 2-clock and 4-clock SDRAMs. almost, differ in how they are laid out and accessed. 2-clock SDRAM each clock signal controls 2 DRAM chips on module 4-clock SDRAM control 4 different chips each. Serial Presence Detect: an EEPROM that contains speed and design information about the module. your board requires SPD... CAS2 vs. CAS3: "CAS" stands for column address strobe, main signals used in accessing DRAM chips; "CAS2" and "CAS3" used to distinguish slight variants in SDRAM modules. "2" and "3" refer to the latency of the CAS line, the terms should be "CL2" and "CL3". Packaging Concerns: To make matters even more confusing, SDRAM usually comes in DIMM packaging, which itself comes in several different formats (buffered and unbuffered, 3.3 volts and 5 volts). Mixing DRAM Speeds PCs read a certain bit width of memory at a time, typically 32 or 64, memory making up this width is called a bank. PCs always read data from more than one chip at a time only use the same type and speed of memory within a bank. also use the same technology-- never mix EDO and FPM memory (for example) within a bank. Slowest Memory Put in the First Bank: Some memory systems automatically look at the speed of the memory in the first bank when setting the timing. Memory Bus Speed and Required DRAM Speed Processor Memory Bus Usual Required DRAM Usual DRAM Technology Generation Speed Speed (ns) First, Second 4.77-20 100-120 Conventional 100-120 Third, Fourth 16-40 70-100 Conventional, Page Mode, FPM,EDO Fifth, Sixth 50-100 8-10 (SDRAM) 50-70 FPM, EDO, BEDO, SDRAM (Asynchronous) Future 125+ ? SDRAM, DDR SDRAM, DRDRAM, SLDRAM, Other? System Timing and Wait States true speed that the memory subsystem runs referred to as the system timing. using a number of settings in the BIOS setup program, normally specified as the number of clock cycles EDO memory is faster than FPM. Burst Mode Access and Timing memory is stored as a matrix; you must address it by supplying the row and column usually, read 32 or 64 bits at a time (64 on modern PCs). row address sent to memory, followed by column address. the data itself is transferred. first access to memory takes a-usually from 4 to 7 clock called the latency of the memory. Four consecutive 64-bit pieces of memory are read one after the other (256 bits or 32 bytes). called burst mode access or bursting. Modern caches also do this type of burst access. timing of burst mode access is generally stated using this type of shorthand: "x-y-y-y". The first ("x") number of clock cycles do first 64-bit read/write. other numbers are how many clock cycles to do the second, third and fourth reads/writes. "5-2-2-2", which means 11 clock cycles for whole burst. System Timing and Memory Technologies FPM fast page mode regular in most Pentium systems, (FPM) memory burst cycle time of 3 clock cycles, while EDO extended data out (EDO) memory will run with only 2 clock cycles. SDRAM will usually require only one clock cycle when bursting. DRAM Technologies and Relative Performance has unfortunately become an exercise in buzzword juggling BIOS Settings Advanced Chipset Features Most settings are associated with fine-tuning control over the system cache, memory, and I/O buses, to optimize performance. ROM Read-Only Memory (ROM) Permanence: called non-volatile storage. You are not going to find viruses infecting true ROMs, BIOS ROM (EEPROM) chip, commonly called a flash BIOS. is located in a socket on the motherboard usually labelled Award, American Megatrends (AMI),Phoenix BIOS Updates and The Flash BIOS only change necessary to support these larger drives many motherboard manufacturers able to expand the capabilities of their boards, BIOS CMOS Memory a very small battery data preserved. T typically 64 bytes, batteries that they use typically last for years. This non-volatile memory is sometimes called NVRAM. ESCD Extended System Configuration Data (ESCD) where BIOS settings are held. to hold configuration information for the hardware in your system. At boot time the BIOS checks this area of memory and if no changes have occurred since the last bootup, it knows it doesn't need to configure anything and skips that portion of the boot process. used communications link between BIOS and operating system Boot Block Many newer systems come with a 4 KB "boot block" program is included as part of the BIOS. job to recover from the BIOS code incorrect or corrupted. Plug and Play BIOS is one of the four major parts of the system whose cooperation is required in order to implement Plug and Play features on a PC. PnP Plug and Play (also called "PnP" for short your PC hardware, BIOS and operating system identify and configure hardware devices automatically. to reduce number of resource conflicts, jumper settings, and manual driver setups Plug and Play developed by Microsoft with cooperation from Intel The four "partners" that must be Plug and Play compliant System Hardware: Peripheral Hardware: The System BIOS: The Operating System: Most of actual work is performed by the system BIOS during the boot process. 1.Create resource table of available IRQs, DMA channels and I/O addresses, excluding reserved system devices. 2.Search identify PnP and non-PnP devices on PCI,ISA buses 3.Load last known system configuration from ESCD area 4.Compare current configuration to last known If they are unchanged, continue with the boot; 5.If configuration new, begin system reconfiguration. 6.Check BIOS settings if any additional system resources 7.Assign resources to PnP cards 8.Update the ESCD area will print "Updating ESCD ... Successful". 9.Continue with the boot. PnP not Non-Plug-and-Play Devices can be used in a PnP system, called legacy devices, "old hardware we have to keep using even though it doesn't have the capabilities we wish it did". :^) they cannot be automatically configured by the BIOS. BIOS deals with non-PnP devices by ignoring them. It simply considers them as "part of the scenery" and avoids any resources they are using. Plug +Play amusing sarcastic name "Plug and Pray" :^) you are essentially turning over control of system configuration to the PC. isn't as smart as the human, or more specifically, the computer isn't as "resourceful" (no pun intended. :^) ). The biggest problems with Plug and Play revolve around its apparent "stubbornness". system seem determined to put a device at a location where you do not want it. BIOS put COM4 conflicting with COM2 serial port. can get quite aggravating to deal with. Standardized Sockets and Slots spurred on by marketing program from Intel itself. Intel with its OverDrive program, promising the availability of upgrade processors to improve performance with no more than change of chip Keying and Orientation many sockets are keyed through asymmetrical pin layouts, so that processor cannot be incorrectly inserted BIOS Settings Warning: The highly prudent will have a backup of hard disk before fiddling with BIOS settings. Date The system date. the correct format; normally this is mm/dd/yy IDE Primary Master where the hard disk parameters are entered for the primary master IDE/ATA device, the first drive in a modern IDE system. Dynamic RAM (DRAM) refresh circuit. Many hundreds of times each second, Memory Access and Access Time A specific procedure is used to control each access to memory, which consists of having the memory controller generate the correct signals to specify which memory location needs to be accessed, a nd then having the data show up on the data bus Speculative Leadoff the first access to memory ("leadoff") by overlapping the start of the read request Interleaving by allowing simultaneous access ROM Shadowing in most PCs, there is a full 384 KB area of RAM in the UMA. When any addresses in the UMA region are used by ROMs, the RAM underlying them is hidden. However, doesn't mean it has to be wasted. access time of ROMs is usually between 120 and 200 ns, compared to system RAM which is typically 50 to 70 ns. RAM is accessed 32 bits at a time, ROMs are usually 16 bits wide. most systems have the ability to "mirror" the ROM code into this RAM to improve performance. called ROM Shadowing,controlled using set BIOparameters HMA High Memory Area (HMA) the first 65,520 bytes (64 KB less 16 bytes) of extended memory. from addresses 100000h to 10FFEFh. the only part of extended memory that can be used by the PC while operating in real mode. Normally in real mode the processor cannot access extended memory at all and must use protected mode or special drivers. Don't confuse high memory area with upper memory area, Intel created the 80286 processor, it supported both protected mode and real mode. in real mode the 80286 was supposed to behave exactly the same as an 8088 or 8086, for compatibility. 80286 does have a 21st address line (it has 24),due to a bug in its design it didn't do the wrap around in the same way as the 8088 when in real mode. used address FFFF:FFFF and came up with 10FFEFh for linear address, kept as 10FFEFh instead of wrapping around to 0FFEFh like on the older CPUs. allowed the first FFEFh of extended memory (100000-10FFEFh) to be accessed by the chip even while still in real mode. This block of memory is the high memory area (HMA). still problem ensuring compatibility of 80286 when in real mode. IBM solved original AT by using spare lines in the keyboard controller chip to manage the 21st address line (called A20 line because address bits are numbered starting with zero). keyboard controller turns off the A20 line when the processor is running in real mode, to allow for full compatibility with the older PCs. It turns it back on when running in protected mode. why sometimes see error message relating to the A20 line when you have a keyboard problem with your PC. Many years later, 640 KB limit of conventional memory quite cramping ability to access an additional 64 KB of memory in real mode was seen as a significant advantage. (People at this time were scratching and clawing to get even 8 KB more conventional memory to let them run large programs that insisted on certain minimums). Microsoft developed a special driver called HIMEM.SYS t allowed A20 line manipulated under software control This allows the high memory area to be put to good use. high memory area is normally used by DOS itself. Specifying "DOS=HIGH" in the DOS system file CONFIG.SYS tells DOS to load a portion of its own code into high memory area instead of conventional memory. frees approximately 45 KB memory for use by programs. final step in institutionalizing this former bug as an official PC feature was removing manipulation of the A20 line from the keyboard controller. was originally a hack anyway the controller used because no better way to do it nothing to do with the keyboard-- FPM Fast Page Mode (FPM) DRAM FPM memory is slightly faster than conventional DRAM. FPM works by sending the row address just once for many accesses to memory in locations near each other FPM DRAM typically allows burst system timings as fast as 5-3-3-3 at 66 MHz. BEDO Burst Extended Data Out (BEDO) DRAM Burst EDO or BEDO memory EDO memory is combined with pipelining technology and special latches to allow for much faster access time than regular EDO. BEDO memory allows use of much higher memory bus speeds BEDO allows system timings of 5-1-1-1 VRAM Video RAM (VRAM) and Other Video DRAM Technologies Modern video adapters use specialized RAM separated from the main system memory. Cache A 512 KB level 2 cache, caching 64 MB of system memory, can supply information s 90-95% of the time. Programs tend to spend large periods of time working in one small area of the code, often performing the same work many times over and over with slightly different data, because of "loops", cache is programmed (in hardware) to hold recently-accessed memory locations each of these instructions saved in cache after being loaded from memory The next time the processor wants to use the same instruction, it will check the cache and load it from cache cache Pronounced cash, smart caching system recognize certain types of frequently used data. RAM disk RAM that has been configured to simulate a disk drive. You can access files on a RAM disk as you would real disk approximately a thousand times