=====================FEEDTHUR_ERRORS========================
                            ___
                           |VIN|
                           |___|     ___
                          ___|_     |CTL|
                         |  _| |    |___|     TEST SCHEMATIC A19
                         | |_| |   ___|_
                        _|_____|__|  _| |
                       |__________  |_| |
                         |  _  |  |_____|    
                         | |_| |
                         |___|_|      ___
                             |_______|OUT|
                            _|_      |___|
                            ___
                            _|_
                            /// 
                      
                      When a switch turns off in the case of a sample and hold
                      circuit, the charge in the gate region which forms the channel
                      tends to migrate towards the gate and source region provided
                      the transit time of charge across the gate is small compared
                      to the time it takes for the gate to be pulled down. It has 
                      been recommended that the channel length be made minimum to 
                      prevent charge being left under the gate when the channel goes
                      away. 
                      
                              ON -> Off
                                _|__                   VCC =3
                                ____   2.6/1
                        ___    |    |            ___
                       |   |___|    V___________|   |   VIN   VFT_mV
                       |___|             |      |___|    0     -5  
                        _|_             _|_              .5    -3.8
                       /VIN\            ___              1     -2.4
                       \___/             | 1pf           1.5   -1.14
                         |               |               2      0ff
                        _|_             _|_
                        ///             ///
                      
                       
                      The troubles with "charge conservation models" are well know by the
                      CAD group. The trouble with MOS devices is their channel capacitance
                      is not linear. Other test circuitry has shown that  for at least
                      for NMOS devices, the models work well enough to keep the ADC designers
                      marginally happy. First order, the  offset introduced to a sample and
                      hold capacitor is a function of overdrive voltage. The simulated 
                      results are shown above and they are in the same order of magnitude
                      is experienced in the ADC0831(mask making offset included?)
                      
                             ___
                            |VIN|            __________________________
                            |___|      ___  |               ___        |       ___
                            ___|_     |CTL| |    _____     |DUM|    ___|_     |CTL|
                           |  _| |    |___| |   |  _  |    |___|   |  _| |    |___|
                        ___|_|_| |   ___|_  |___|_|_| |   ___|_    | |_| |   ___|_
                       |  _|_____|__|  _| | |  _|_____|__|  _| |  _|_____|__|  _| |
                       | |__________  |_| | | |__________  |_| | |__________  |_| |
                       |   |  _  |  |_____| |   |  _  |  |_____|   |  _  |  |_____|     
                       |   | |_| |    ______|___|_|_| |            | |_| |          
                       |   |___|_|   |  ___     |_____|            |___|_|     
                       |       |_____|_|OUT|                           |
                       |      _|_      |___|      _____________________|
                       |      ___                |
                       |      _|_                |
                       |      ///                |
                       |_________________________|
                      
                      This charge injection due to the channel turning off is cancelled by 
                      by turning on a "dummy" transistor which is intended to have the exact 
                      opposite effect. Because drain and sources may not be proccessed equally,
                      a layout as is shown above may be of use 
                      
                      
                              ON -> Off     OFF -> ON
                                _|__          _|__             VCC =3
                                ____   2.6/1  ____
                        ___    |    |  2X    |    |    ___
                       |   |___|    V________|____V___|   |     VIN   VFT_mV   VFT2_mv
                       |___|             |            |___|      0     -9.4    .43
                        _|_             _|_    2.6/1            .5     -7.1    .22
                       /VIN\            ___                      1     -4.7    .05
                       \___/             | 1pf                   1.5   -2.3    .008
                         |               |                       2      0ff
                        _|_             _|_
                        ///             ///
                      
                      Another problem with the dummy is if you turn it on at the same 
                      time you turn off the channel, some of the cancellation charge 
                      may escape through the channel. Add a little delay. And above are
                      the results. VFT_mV is the injected offset after the channel
                      opens.  VFT2_mV is the is the injected offset after the dummy 
                      turns on. Notice that the cancellation is not perfect. 
                      
                      
                                  ON -> Off     OFF -> ON
                                    _|__          _|__             VCC =3
                                    ____   2.6/1  ____
                        ___        |    |  2X    |    |    ___
                       |   |__/\  _|    V________|____V___|   |     VIN   VFT_mV   VFT2_mv
                       |___|    \/ |       |              |___|      0     -9.7     .18
                        _|_       _|_     _|_    2.6/1              .5     -7.3     .002
                       /VIN\   1K ___     ___                        1     -4.8    -.002
                       \___/       |1pf    | 1pf                    1.5    -2.2    -.007
                         |         |       |                         2      0ff
                        _|_       _|_     _|_
                        ///       ///     ///
                      
                      As has been described in papers, the channel charge tends to go to the
                      lower impedance. Putting equal size capacitors on each end of the channel
                      and putting a 1k resistor in series greatly improves the cancellation. 
                      
                      
                      
                                  ON -> Off     OFF -> ON
                                    _|__          _|__             VCC =3
                                    ____   2.6/1  ____
                        ___        |    |  2X    |    |    ___
                       |   |__/\  _|    V________|____V___|   |     VIN   VFT_mV   VFT2_mv
                       |___|    \/ |       |              |___|      0     -2.0     .002
                        _|_       _|_     _|_    2.6/1              .5     -1.43   -.001
                       /VIN\   1K ___     ___                        1     -.96    -.001
                       \___/       |5pf    | 5pf                     1.5   -0.4     .001
                         |         |       |                         2      0ff
                        _|_       _|_     _|_
                        ///       ///     ///
                      
                      With larger caps, the cancellation appears to be near perfect. But 
                      again the simulated results need to be taken with a grain of salt. 
                      First off, a spice simulator can fail to obey charge conservation
                      in the transient mode even with linear capacitors. Second, how well
                      two MOS devices match is also an important question to which 
                      test geometries will be added to the next test die.
                      
                      
                      
                                  ON -> Off     OFF -> ON
                                    _|__          _|__             VCC =3
                                    ____   2.6/1  ____
                        ___        |    ^  2X    |    ^    ___
                       |   |__/\  _|    |________|____|___|   |     VIN   VFT_mV   VFT2_mv
                       |___|    \/ |       |              |___|      3     none     none
                        _|_       _|_     _|_    2.6/1               2     none     none
                       /VIN\   1K ___     ___                        1     Off 
                       \___/       |.5pf   | .5pf                     
                         |         |       |                          
                        _|_       _|_     _|_        MODELs have a problem?
                        ///       ///     ///
                      
                      To wrap things up, the same tests were performed on the PMOS devices
                      and their simulation says they have no feedthru at all. I guess the
                      ADC designer typically use NMOS devices for their critical switching
                      anyway. 
                      
                      In conclusion, laying out arrays of both NMOS and PMOS sample and
                      hold switches in both X and Y directions hopefully can provide the 
                      answers to the question of how good of a sample and hold can we make. 
                      { 12Bit ADC anybody? }
                      
                      
                      
                      152nA = 171K = 52nV 
                      
                      1.5v -1.219  3v 1.247   1.5/500K = 3uA  = 28uV  about  10 ohms
                      1.5  -1.51   3v 1375    1.5/1K =  1.5mA = 135uV about  .1 ohms
                      1.5  -1.112   3v 1313   1.5/10K =  150uA = 201uV about 1.3 ohms
                      1.5  -1.06   3v 1475    1.5/100 =  15mA = 451uV about  30m ohms
                      1mV over +/-150mA  at 10 ohms is 3mohms 
                      current limit 900mA
                      
                      bW = 30k 1000pF  Q = 7 stable   more s
                      87kHz 100pf Q = 5          10K load= q=2  open Q = 7
                      100Khz bw at 10pf q = 2
                      
                      
                      Vcm  R277  R278  R275  R276   Q324 Q323 Q321 Q322 Voffu
                      0    1000  1000  1000  1000   1     1   1     1   -194.9
                      2.50 1000  1000  1000  1000   1     1   1     1   -197.6
                      2.50 1000  1030  1000  1000   1     1   1     1   -100.8
                      2.50 1000  1100  1000  1000   1     1   1     1    327.8
                      0    1000  1100  1000  1000   1     1   1     1    320.3
                      0    1000  1100  1000  1000   1.04  1   1     1   -999.3
                      0    1000  1000  1000  1000   1.04  1   1     1  -1418.3
                      0    1000  1400  1000  1000   1.04  1   1     1     36.6
                      2.5  1000  1400  1000  1000   1.04  1   1     1    109.9
                      5    1000  1400  1000  1000   1.04  1   1     1     836
                      5    1000  1400  1000  1000   1.04  1   1     1.04 1672
                      5    1000  1400  1000  1500   1.04  1   1     1.04   15
                      2.5  1000  1400  1000  1500   1.04  1   1     1.04  -904
                      0    1000  1400  1000  1500   1.04  1   1     1.04  -906
                      0    1000  1600  1000  1500   1.04  1   1     1.04  -83
                      2.5  1000  1600  1000  1500   1.04  1   1     1.04  -65.3
                      2.5  1000  1600  1000  1500   1.04  1   1     1.04  -388
                      5    1000  1600  1000  1500   1.04  1   1     1.04  -388