======================SILICON_ESD=============================== Human Body Model HBM ___ Rs => 1.5K |Vs |__/\ ____ ___/\ ____ |___| \/ \ \/ | Auto = 4K to 20K | _|_ 2000V _|_ |DUT| ___ 100pF |___| 2KV = perception pain | | ___ | | |GND|____________|___________| tau = 150ns |___| I = 2A @ VS=2K 2A | 10ns 15% ringing | ~~-_ | / -_ | / -_ |/____________ time constant 150ns Number devices Min 3 each stress test each pin zap each to VCC shorted to GND Class 1 0 to 1999V Class 2 2000V to 3999V Class 3 4000V or above Machine Model MM Like handler Japanenes model 750nH + 25ohms ___ Rs => _ _ _ |Vs |__/\ ____ ___/ \/ \/ \__/\ _ |___| \/ \ () () \/ | | _|_ 200V _|_ |DUT| ___ 200pF |___| | | ___ | | |GND|____________|___________________| tau = 50ns |___| I = 1.7A @ VS=200V | 30ns | : 1.7A | _--_ : | / \: __ |/______|____/_ \__/ time constant 50ns Charge Device Model CDM ___ Rs => 1ohms |Vs |__/\ __ __/\ _ |___| \/ | ___ / \/ | Charge each pin |_|DUT|__| | then short to ground 1500V |___| | ___ 200pF | Like factories | | ___ | | |GND|____________|_______________| |___| I = 7->20A @ VS=1500V | | 1.7A | _--_ 7 -> 20A <1ns | / \ |/______|____ time constant 400ps ESD HBM TESTER ___/\ __ | \/ | |__||_____| DUT 23nH| ||0.8pF| 6.3nH ___ _ _ _ | _ _ _ | _ _ _ ___ | |__/ \/ \/ \|/ \/ \/ \|/ \/ \/ \_______________| | |___| | () () () () () () | | _|_ |___| _|_ 2.2nH _|_ | 1.5K ___ ___9.3pF ___ |_/\ ___| 0.7pF | 6.3nH | \/ _|_ 100pF ___ | _ _ _ _ _ _ _ _ _ | 2.5pF ___ ___ | |_|/ \/ \/ \_/ \/ \/ \_/ \/ \/ \|___________|__| | |___| () () | () () | () () |___| | 6.3nH | 0.8pF| 6.3nH tester gnd _|_ |___||____| /// | || | |_/\ ____| ESD HBM TESTER simulator \/ ----------------------Common_failures-------------------- High_field Oxide rupture most common small crater formed under gate material can happen at sharp corners Localize_heat filamentation most common silicon melts, Si resist down 1/30, thermal runaway refered to as second breakdown In bipolar BE most common increase in reserve leakage current of pn junction worst case junction shorted. Junction spiking the same except melting includes aluminum which lowers melting point to 577C as oppose to 1415C for silicon. high_current_density Thin film fusing common oxide charging least common.. because oxide damage happens too Contamination Bakeable leakage at input Hot electrons Bakeable leakage at output rho 85 mohms/sq thick 0.5u metal melts 653 J/gm at 653 C metal melted 1048 J/gm at 660 C metal vaporize 3172 J/gm at 2476 C width J/gm 10u 10,000 15u 2,177 20u 672 High_field ^ /|\ I | physical change in | oxide microstructure c | / u | |_______________ Rupture point r | Dead | r | | e | | Non destructive n | | Conduction t |______________|______________\ Capacitor Voltage / Most common is rupture of oxide which has a IV curve as is shown above. ______________ ___ _|_ | | | High field /// | |___| Oxide rupture most common ________| | Source| Gate | Drain | small crater .1u under gate __|__ __|___ __|__ ______|_ _|__|_____v|__|_ _|______ | N+ | | N+ | OXIDE DAMAGE \________/ \________/ 1nA -> 10uA Substrate possible to see this damage. damage is also sensitive to the oxide thickness and the amount of time voltage is applied. Oxide Breakdown versus time and thickness 1sec ................................... | . . . | 55A . 100A . 200A . | . . . | . . . | . . . 1msec |......55A........100A........200A... | . . . | . . . | 55A. 100A . 200A . | . . . | . . . 1usec |..........55A........100A......200A.. | . . . | .55A 100A . | . 55A . 100A 200A | . . . | . . . |____________________________________ 0V 10V 20V 30V Breakdown voltage Even before breakdown, the oxide can be modified as is shwon below/ Oxide Degraded 30V .................................... | . BD BD . | . BD TS . | BD TS. . | Break BD TS . . | Down BD . TS . . 20V |.......BD......TS................... | BD . TS . . | BD .TS 10mV Threshold shift. | BD TS . . | BD TS. . . | BD TS . 100nsec Pulse . 10V |...BD.TS............................ | . . . | . . . | . . . | . . . | . . . |____________________________________ 0A 100A 200A 300A Thickness high_current_density ^ /|\ I | | c | Oxide charge injected into oxide u | physical change in oxide microstructure r | r | / e | / Strong Avalanche n | _ t |_______-____________\ Avalanche Voltage / When electrons have lot energy, hot electrons enough energy to penetrate the oxide barrier. ______________ ___ Hi I +d chargeinjection _|_ | | | local heat/oxide rupture /// | |___| ________| | can see small notches Source| Gate | Drain | at drain/gate from hot __|__ __|___ __|__ spots caused byelectron ______|_ _|__|______|__|_ _|__trapped in gate | N+ | `-_ N+ | \________/ \________/ 5u drain spacing to contacts help 1nA -> 10uA Substrate JUNCTION EDGE DAMAGE Having electrons inside the oxide can create localize heat or oxide rupture. Localize_heat ^ /|\ I | | Damage by local heating c | / u | |____ Second Breakdown r | Dead / r | / e | / n | _ t |-______________________\ Foward Diode Voltage / Once silicon melts, all bets are off.resistance drops by a factor of 30 and a small area goes into thermal runaway. ______________ ___ _|_ | | | Localize heat /// | |___| silicon melts ________|___ | Si resist 1/30 Emitter| Base | Collector | thermal runaway __|__ __|__ __|__ _________|_ _|___ __|_ _|_______|_ _|_____ | | | N+ | | | N+ | | | | \________ / Base | \________ / | | \ \| / | | \______________________/ | | _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ | |/ \| \_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ / FILAMENTATION For Bipolar transistors, runnawayoften called second break down. destruction involve a filament in the emitter base junction because where the TC effects are most unstable. ^ /|\ I | | Damage by local heating c | / u | |_______________ Second Breakdown r | Dead | r | / e | / n | _ Breakdown t |_____________-_______________\ Reverse Diode Voltage / ______________ ___ _|_ | | | Localize heat /// | |___| si melts->thermal runaway ________| | al lowers melting to 577C Source| Gate | Drain | __|__ __|___ __|__ JUNCTION SPIKING ______|_ _|__|______|__|_ _|______ | N+| | N+| / | \________/ \___|/___/ / > 50uA Substrate ______________ ___ _|_ | | | Localize heat /// | |___| ________| | Source| Gate | Drain | Can see metal filament hole __|__ __|___ __|__ when etch away metal ______|_ _|__|______|__|_ _|______ | \`------------' / | \ N+ `-------------' N+ | METAL FILAMENTATION \_______/ \________/ 1uA -> 100uA Substrate For MOS devices, if the aluminum melts, the melting point gets much lower and a metal filament can grow and be seen. often time the extra steps taken in processing to reduce hot electrons can also further degrade ESD preformance Silicides reduces contact resistance But lower thresshold preformance because more current flows in a smaller silicide area since the ressistance of silicide to silicon is high. (Drop by 50%) LDD reduces Hot electron degradation LDD also may reduce the area which power is dissipated. Snap_Back_Protection It is the lateral NPN that clamps the ESD voltage. When currents get high enough, enough holes get generated in the substrate to over come the resistance to ground and the NPN goes into the Vceo mode. _____________ ___ _|_ | | | /// | |___| ________| | Source| Gate | Drain | Holes into Base from CB __|__ __|___ __|__ leakage ___|_ _|__|______|__|_ _|_Base/Bulk voltage rises | N+ |---> | N+ |Electrons emit fromemitter \________/--> <++\_______/ Thresshold voltage lowered Substrate ___ | | |___| |_____________ __| | || _| ||___________ _|' NPN __|| | |`-> | ||-> _/\ _| | | | | \/ | |_____|__|___________| _|_ /// One key detail is where the snap back voltage happens. Hopefully maximum oxide voltage is not exceeded before this point is reach. ^ /|\ I | | c | / u | |_______________ Second Breakdown r | Dead | r | / e | SnapBack/ SnapBack n | Voltage|______Thresshold t |_____________________/_______\ Snap Back Breakdown Voltage / The present ESD structure is shown below. PMOS device being used as a capacitor and the gate of the main NMOS is being clamped by another NMOS device. ___ | |___________ |___| | ___ |__________/\ __| | | | | \/ |___| _||<- | 5/5 | | ||____| | | || | | | ||____| | _/\ __| | 6u to drain | \/ | | | |_______ | | |__ | __| | 1/10 || | || 1/95*2 | ||___|__|| | <-|| ||-> | | | |_______|_____________| _|_ /// this structure tends to fail at 1000 volts and tends to pass 2000volts. present guess is the transister snap back happens at too high of an voltage and 2000 volts puts it into snap back sooner. Several experiments done and are in the process of being done. It is known the higher the gate voltage, the sooner the snap back as is shown below. ^ /|\ I | | c | u | r | // r | // e | / |_ Vg>0 n | |___\__ Vg=0 t |____________________/__/________\ Snap Back Breakdown Voltage / ___ _____ __/ Vg\_ ___ _|_ | \___/ | | | /// | | |___| | | | Source| Gate | Drain | Holes into Base __|__ __|___ __|__ from CB leakage __|_ _|__|______|__|_ _|_Base/Bulk voltage rises | N+ |---> | N+ |Electronsemitfrom emitter \________/--> <++\________/ Thresshold voltage lowered Substrate ___ ___ | |___________ _______________/\ _| | |___| | | \/ |___| oxide is 15V _|_/ | zener / ^ |_______ 6.6V +1.4V = 8V thresshold 70pA /_\ | | @ 1/2ohm impedance leakage | _| _| (1Kohm) |_|' 20X |' 200X Vceo 6.6V | |`->____| Vcbo 16V | | |`-> \ \ | NPN leakage less than 1pA 20K / / 8K | \ \ | |______|_____| _|_ /// using a darlington, a very small size zener can be used to drive the input. leakage current of NPNs in process is low, input leakage dominated by the zener leakage should be about 70pA at room. over temperature suggest this leakage only increases a factor of ten over temp. ___ ___ | |_________________________/\ _| | To |___| | | \/ |___| oxide is 15V _|_/ | zener / ^ | 6.6V +1.4V => 8V @ 1/2ohm impedance 70pA /_\ | oxide is 15V leakage | | _|_ | \ / | _v_ | | | _|_ _|_ \ / ^ _v_ /_\ |_____| | \ 1/2ohm / 1/2ohm \ | _|_ /// Simulations model the clamps as is shown above. impedance is about 1/2 an ohm. The clamp is attempting to limit amount of voltage to under the gate oxide breakdown voltage of 13-15volts given below. At 2000volts expect 1.3A HBM At 200volts expect 1.7A MM Simulations with clamps good results for ESD voltages as high as 8000volts HBM and 500volts MM. Base Emitter Collector __|__ __|__ __|__ ______|_ _|__________|_ _|_____|_ _|____ | | | P+ | | -/\/\- N+ | | | N+ | | | \ \_____/Base\___________/ / \_____/ | | \ -/\/\- / | | | | \______________________/ NWELL| | | | _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ | _ | _ | |/ N BURIED LAYER \| \ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _/ N+ 57-93ohm/sq base 1150 -1530/sq pinch 7K/sq beta 72 +/-10% 7000/72 is about 100ohms/sq (higher beta = higher pinch) But there are several extra details to using the vertical NPN besides the fact its simulations say it should work. The energy will appear at collector base junction of NPN. But the NPN can be layed out like they are for Power amplifiers such emitter current is spread out over as much silicon real estate as possible. IR drop in base of transister about same magnitude and directions as is IR drop in emitter. Providing some distance between the base and emitter contacts is using the emitter as a degeneration resistors attempting to spread the emitter current over as much of the emitter area as possible. ___________ ___ _|_ | | | /// | |___| ________| | Source| Gate | Drain | Holes into Base from __|__ __|___ __|__ CB leakage ___|_ _|__|______|__|_ _|___Base/Bulk voltage rises | N+ |---> | N+ |Electrons emit fromemitter \________/--> <++\________/ Thresshold voltage lowered Substrate present NMOS is also using a NPN as a clamp. But NPN is Lateral NPN which has a snapbake voltage as is shown below. lateral action may not involve as silicon area for the given size of drain or source die area. ^ /|\ I | | c | / u | |_______________ Second Breakdown r | Dead | r | / e | SnapBack/ SnapBack n | Voltage|______Thresshold t |_____________________/_______\ Snap Back Breakdown Voltage / vertical NPNhave a snap back voltage in that the Vceo is only 6.6volts. emitter base resistor needs across the 200X NPN to keep its breakdown close to Vcbo Once this NPN is drawing Amps, this 8kohm resister i to matter much. ___ ___ | |___________ _______________/\ _| | To |___| | | \/ |___| oxide is 15V _|_/ | zener / ^ |_______ 6.6V +1.4V 8V thresshold 70pA /_\ | | @ 1/2ohm impedance leakage | _| _| (1Kohm) |_|' 20X |' 200X Vceo 6.6V | |`->____| Vcbo 16 | | |`-> \ \ | NPN leakage less than 1pA 20K / / 8K | \ \ | |______|_____| _|_ /// layout of Main NPN is shown below. whole clamp die area slightly less than present ESD structure. Collector Emitter Base Emitter Collector _|_ _|_ _|_ _|_ _|_ |_ _|_____|_ _|_________|_ _|__________|_ _|_____|_ _|____ | N+ || | N+ -/\/\- | | P+ | |-/\/\- N+ | | | N+ | | \___/ \ \_________/ \___/Base\_________/ / \___/ | | | \ -/\/\- -/\/\- / | | | | | \_________________________________/ | | _|_ |_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ | _|_ _| / N BURIED LAYER \ \ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _/ ___ ___ | |___________ ____________________/\ _| | To |___| | | | \/ |___| Circuit _|_/ | / zener / ^ | \ 70pA /_\ | / 100/72 = 1.4ohm = RC leakage | _| _| 42mA/contact @ 32 contact@1.2A (1Kohm) |_|' 20X |' 200X | |`->____| | | |`-> \ \ \ 20K / / 8K / (14+.3)/72 = 0.2ohms = RE \ \ \ 17mA/contact @ 72 contact @1.2A |______|_____| _|_ /// BL = 30ohm/sq => 30*7/90*2 => 1.2ohms sink = 10/sqr => 10/72 => .14ohms base = 3000/32 => 100 met1 = 40mohm/sq => 40m*90/5 => .72ohms met2 = 25mohm/sq => 25m*90/17 = .140ohms n+ = 14 0hms/contact , P+= 8 ohms/contact via = .3 ohms/contact collecter/sub diode = 140ohms/82contacts => 1.70ohms not real obvious that the 1/2 clamp can not be built. performance of the clamp may now be dominated by metal routing inside die as is shown below.metal IR drop from any pad to ground is also around 1/2 . ____________________________________ | __________________ | | ____ | ______________ | ____ | | | |_| |<===1.3ohms==>| |_| | | | | _ | | _ VCC | | | |____| | | | | |____| | | ____ | | | | ____ | | | |_| | | |_| | | | | _ | | _ GND | | | |____| | | | | |____| | | ____ | | | | ____ | | | |_| | | |_| | | | | _ | | _ | | | |____| | |______________| | |____| | | |__________________| | |____________________________________|