Verilog Templates (On Going Development)

//=========================hello.vl====================
module                     main;
initial
begin
$display("Hello, World");
$finish ;
end
endmodule

donsauer$ cd /Users/donsauer/Documents/KEY/KEY0/verilog     // drag folder into terminal
donsauer$ ./iverilog hello.vl                              // produces a.out
donsauer$ ./a.out                                           // runs a.out
           Hello, World

//========================counter_Plus_Test.v====================

module            test;
reg                       reset = 0;            /* Make a reset that pulses once. */
initial begin
# 17                      reset = 1;
# 11                      reset = 0;
# 29                      reset = 1;
# 11                      reset = 0;
# 100                     $stop;
end
reg                       clk = 0;
always #5                 clk = !clk;    /* Make a regular pulsing clock. */
wire [7:0]                value;
counter                   c1 (    value, clk, reset);
initial
$monitor(                "At time %t, value = %h (%0d)", $time, value, value);
endmodule

module            counter( out, clk, reset);
parameter WIDTH =       8;
output [WIDTH-1 : 0]                out;
input                                     clk, reset ;
reg [WIDTH-1 : 0]         out;
wire                                      clk, reset ;
always                    @(posedge       clk         )
out <=                    out + 1;
always                    @reset
if                        (reset)
assign                    out = 0;
else
deassign                  out;
endmodule

//========================
donsauer$ ./iverilog counter_Plus_Test.v                   // produces a.out
donsauer$ ./a.out                                           // runs a.out
At time                    0, value = xx (x)
At time                   17, value = 00 (0)
At time                   35, value = 01 (1)
At time                   45, value = 02 (2)
At time                   55, value = 03 (3)
At time                   57, value = 00 (0)
At time                   75, value = 01 (1)
At time                   85, value = 02 (2)
At time                   95, value = 03 (3)
At time                  105, value = 04 (4)
At time                  115, value = 05 (5)
At time                  125, value = 06 (6)
At time                  135, value = 07 (7)
At time                  145, value = 08 (8)
At time                  155, value = 09 (9)
At time                  165, value = 0a (10)
** VVP Stop(0) **
** Current simulation time is 168 ticks.

> finish
** Continue **

//========================counter_Plus_Test.v===============================
module            test;
reg                   reset;
reg                   clk;
wire [7:0]                value;
initial               begin
$dumpfile(               "counter_Plus_Test2.vcd");
$dumpvars(                0, test);
# 1 clk =                0;
# 17 reset =              1;
# 11 reset =          0;
# 19 reset =          1;
# 31 reset =          0;
# 100                 $finish;
end
always #5               clk =!clk;
counter                 c1 (       value, clk, reset);
initial
$monitor(            "At time %t, value = %h (%0d)", $time, value, value);
endmodule

module                  counter( out,   clk, reset);
parameter WIDTH =         8;
output [WIDTH-1:0]             out;
input                                     clk, reset ;
reg [WIDTH-1 : 0]              out;
wire                                  clk, reset ;
always                @(posedge         clk         )
out <=              out + 1;
always            @reset
if                   (reset)
assign out =        0;
else
deassign            out;
endmodule

//========================RUN_GTKWave===========================
donsauer$   ./iverilog counter_Plus_Test2.v                   // produces a.out
donsauer$   ./a.out                                            // creates vcd
VCD info: dumpfile counter_Plus_Test.vcd opened for output.
At time                    0, value = xx (x)
At time                   18, value = 00 (0)
At time                   35, value = 01 (1)
At time                   45, value = 02 (2)
At time                   48, value = 00 (0)
At time                   85, value = 01 (1)
At time                   95, value = 02 (2)
At time                  105, value = 03 (3)
At time                  115, value = 04 (4)
At time                  125, value = 05 (5)
At time                  135, value = 06 (6)
At time                  145, value = 07 (7)
At time                  155, value = 08 (8)
At time                  165, value = 09 (9)
At time                  175, value = 0a (10)
donsauer$   PATH=${PATH}:/Developer/Simulator/GTKwave/bin
donsauer$   vertex counter_Plus_Test2.v -emitstems >counter_Plus_Test2.stems   //makes des.stems
donsauer$   gtkwave -o -t counter_Plus_Test2.stems counter_Plus_Test2.vcd counter_Plus_Test2.sav &
// opens wave viewer
//========================RUN_GTKWave===========================

//========================SELECT_SIGNALS===========================

//========================VIEW_OUTPUT===========================